The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application Nos. 99-18268 and 99-43784, respectively filed on May 20, 1999 and Oct. 11, 1999.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an isolation layer of improved structure, a method of forming the isolation layer, and a method of forming a source/drain region using the isolation layer.
2. Description of the Related Art
As the integration density of semiconductor devices increases, isolation techniques for electrically isolating adjacent transistors from each other become more important. A local oxidation of silicon (LOCOS) process is a typical isolation technique. However, the LOCOS process is known to be unsuitable for highly integrated semiconductor devices having a design rule less than or equal to 0.5 xcexcm. Therefore, a trench isolation technique involving the formation of a trench in a predetermined region of a semiconductor substrate using a photolithography process and the formation of an isolation layer by filling the trench with an insulating material can be used.
The aspect ratio of trenches formed using conventional trench isolation techniques has recently been increased to be greater than or equal to 3, in order to keep up with the increasing integration density of semiconductor devices. As a result, trench isolation causes problems. Namely, when a trench having aspect ratio greater than or equal to 3 is filled with insulating material using an established deposition method such as a chemical vapor deposition (CVD) method, an overhang phenomenon occurs at the entrance to the trench. Accordingly, a void is formed in the trench. When a trench isolation layer is formed by performing a planarizing process such as a chemical mechanical polishing (CMP) process in a following step, the void formed in the trench may be opened. The opening of the void can reduce the reliability of the semiconductor device. To be specific, a process of forming a gate electrode may be performed after forming the trench isolation layer. At this time, a bridge occurs between adjacent gate electrodes since the opened void formed in the trench is filled with a conductive material such as conductive polysilicon during formation of the gate electrode.
Therefore, a method of filling the trench with a material such as undoped silicate glass (USG) having excellent gap-filling characteristics has recently been used. However, even with the use of special gap-filling materials, when the aspect ratio of the trench exceeds certain limits, it is not possible to prevent a void from occurring.
Also, when the aspect ratio of the trench increases, problems are caused during a wide-region planarizing process which must be performed in order to complete the formation of the isolation layer. In conventional trench isolation techniques, it is usual to planarize the entire surface of the semiconductor substrate after filling the trench that is formed by a photolithography process with insulating material. When the aspect ratio of the trench increases, a severe step difference is formed on the entire surface of the semiconductor substrate on which the insulating material is deposited. Therefore, it is not possible to obtain a desired degree of planarization even though the entire surface of the semiconductor substrate is wide-region planarized.
After the trench isolation layer is formed according to conventional technology, a semiconductor device such as an MOS transistor is formed on an active region defined by the isolation layer. Namely, a gate electrode is formed by interposing a gate oxide layer on the active region and source/drain regions are formed on both sides of the gate electrode. In the case of a semiconductor device having a design rule less than or equal to 0.2 xcexcm, the source/drain region is formed to be thin in order to improve the operating characteristics of the semiconductor device. In addition, a silicide layer is formed by performing a salicide process on the gate electrode and the source/drain region in order to reduce the signal delay time of the semiconductor device. When the silicide layer is formed on the source/drain region by performing the salicide process, junction leakage current becomes greater at the boundary between the isolation layer and a junction region than if the salicide process had not been performed. In order to solve this problem, a method of forming the source/drain region as elevated above the semiconductor substrate and then performing the salicide process on the elevated source/drain region has recently been suggested. However, it is not possible to reduce the junction leakage current below the desired value even though the salicide process is performed after forming the elevated source/drain region.
The above problems of the conventional method of forming the trench isolation layer will now be described with reference to FIGS. 1A through 2C.
Referring to FIG. 1A, after forming a trench 12 in a predetermined portion of a semiconductor substrate 10, the trench 12 is filled with a gap-filling dielectric layer 14. For example, the trench 12 can be filled with a silicon oxide layer formed on the entire surface of the semiconductor substrate 10 using a CVD method. As mentioned before, when the aspect ratio of the trench 12 is greater than or equal to 3, an overhang phenomenon occurs at the entrance to the trench 12 as the deposition process proceeds. As a result, a void 16 is formed in the trench 12.
Referring to FIG. 1B, a trench isolation layer 14 is formed by planarizing the entire surface of the semiconductor substrate 10 using, for example, a CMP method. The void formed in the trench isolation layer 14 is opened during the planarizing process. As a result, in a next step of forming a gate with a gate electrode material, the void is filled with the gate electrode material, so that a bridge is created between adjacent gate electrodes.
FIG. 2A is a plan view showing a portion of the semiconductor substrate 10 after forming trench isolation layers A, gate electrodes B, and active regions C. FIG. 2B is a sectional view taken along the line X-Xxe2x80x2 of FIG. 2A. Referring to FIG. 2A and FIG. 2B, the active regions C are defined by forming the trench isolation layers A in predetermined portions of the semiconductor substrate 10. A void 16 having an upper portion that is opened is formed in the trench isolation layer A. The gate electrodes B under which the gate oxide layer is interposed are formed by sequentially forming the gate oxide layer (not shown) and the polysilicon layer on the semiconductor substrate 10 and performing a photolithography process. At this time, the void 16 having an upper portion that is opened is filled with the conductive material, for example, polysilicon 18 which forms the gate electrode B. Furthermore, the polysilicon inside the void 16 is not completely removed in the photolithography process used to pattern the gate electrodes. This results in the formation of the bridge I between the adjacent gate electrodes B.
Referring to FIG. 2C, which is a sectional view taken along the line Y-Yxe2x80x2 of FIG. 2A, the bridge I generated between the adjacent gate electrodes B is clearly visible. The void 16 having an upper portion that is opened and which is formed in the trench isolation layer A is filled with polysilicon 18. Accordingly, the bridge I is formed between the adjacent gate electrodes B. This reduces the reliability of the semiconductor device.
The problems of the conventional method of forming the elevated salicide source/drain region will now be described with reference to FIGS. 3 through 6. Referring to FIG. 3, a trench isolation layer 20 is formed on the semiconductor substrate 10. A gate electrode pattern G including a gate oxide layer 21, a gate electrode 22, and a side-wall spacer 23 is formed on an active region defined by the trench isolation layer 20. A layer of semiconductor material 24 such as silicon is selectively grown on active regions on both sides of the gate electrode pattern G and on the gate electrode 22. Referring to FIG. 4, elevated source/drain regions 25 are formed by implanting conductive impurities such as n-type impurities onto the entire surface of the substrate 10 using the gate electrode pattern G as an ion implantation mask. At this time, a layer of semiconductor material 24xe2x80x2 containing impurities is formed on the gate electrode 22.
Referring to FIG. 5, silicide layers 26 are formed on the elevated source/drain regions 25 and on the gate electrode 22 by performing the salicide process. Namely, a layer of transition metal (not shown) is deposited on the entire surface of the semiconductor substrate 10, and then a portion of the layer of transition metal is changed into silicide by means of a thermal process. The transition metal which is not changed into the silicide layers 26 is removed. When the silicide layers 26 are formed on the elevated source/drain regions 25 according to the conventional technology, the silicide layer 26 can be so formed as to be extended into the boundary between the isolation layer 20 and the source/drain region 25 as shown in II of FIG. 5, thus generating a junction leakage current. That is, the silicide layer 26 is formed to be thick at the boundary between the trench isolation layer 20 and the source/drain region 25, since the transition metal deposited at the boundary of the trench isolation layer 20 and the elevated source/drain region 25 operates as a surplus silicide layer source. Accordingly, the junction leakage current characteristic of the semiconductor device deteriorates, thus increasing the power consumption of the semiconductor device.
The present invention is therefore directed to a method of forming on isolation layer which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is therefore an object of the present invention to provide a method of forming an isolation layer by which it is possible to prevent the generation of a void in the isolation layer.
It is another object of the present invention to provide a method of forming a source/drain region whereby it is possible to reduce junction leakage current generated at the boundary between the isolation layer and an active region.
It is another object of the present invention to provide a semiconductor device including an isolation layer having improved structure.
Accordingly, to achieve the first object, in a method of forming T-shaped isolation layers according to an aspect of the present invention, narrow trench regions, each of which having a first width and a first depth, are formed by etching predetermined portions of a semiconductor substrate. A first gap-filling dielectric layer for filling the narrow trench regions is formed. Wide trench regions, each of which having a second width which is greater than the first width and a second depth which is less than the first depth of the narrow trench regions, are formed in the upper parts of the narrow trench regions. T-shaped isolation layers are formed by forming a second gap-filling dielectric layer for filling the wide trench regions.
In the step of forming the narrow trench regions, a first mask pattern for exposing regions of the semiconductor substrate, of a predetermined width, is formed by sequentially stacking a first insulating layer pattern and a second insulating layer pattern having a large etching selectivity with respect to the first insulating layer pattern. Spacers are formed on the side walls of the first mask pattern with the same material as the second insulating layer pattern so that the width of the lower portions of the spacers corresponds to the first width. A second mask pattern for filling the space bounded by the exposed surface of the semiconductor substrate and the spacers is formed with the same material as the first insulating layer pattern. The spacers and the second insulating layer pattern of the first mask pattern are removed. Narrow trench regions having the first width and the first depth are formed by etching the semiconductor substrate using the first insulating layer pattern of the first mask pattern and the second mask pattern as etching masks.
A third mask pattern for exposing regions of the first gap-filling dielectric layer, each of which having the second width and being centered on the regions having the first width, is formed. Wide trench regions having a second width greater than the first width and a second depth less than the first depth of the narrow width trench regions are formed by etching the first gap-filling dielectric layer and the semiconductor substrate using the third mask pattern as an etching mask.
The first gap-filling dielectric layer is preferably formed by a thermal oxidation method.
In a method of forming T-shaped isolation layers according to another aspect of the present invention, a mask pattern for exposing regions of the upper surface of a semiconductor substrate, each of which having a first width, is formed. Wide trench regions having the first width and a first depth are formed by etching the semiconductor substrate using the mask pattern as an etching mask. Spacers are formed on the side walls of the wide trench regions and the side walls of the mask pattern. Narrow width trench regions having a second width less than the first width and a second depth greater than the first depth are formed by etching the semiconductor substrate using the spacers and the mask pattern as an etching mask. T-shaped isolation layers are formed by filling the narrow width trench regions and the wide trench regions with a dielectric material.
The insulating layer pattern and the spacers may be removed before filling the narrow width trench regions and the wide width trench regions with the dielectric material.
To achieve the second object, in a method of forming elevated salicide source/drain regions, T-shaped isolation layers which have narrow trench regions defined by a first width and a first depth in the lower portions thereof and wide trench regions defined by a second width greater than the first width and a second depth less than the first depth in the upper portions thereof are formed. A gate electrode pattern is formed with a gate oxide layer, gate electrodes, and spacers on an active region defined by the T-shaped isolation layers. A semiconductor material layer is grown on the active regions exposed on both sides of the gate electrode pattern and on the gate electrodes. Elevated source/drain regions are formed by implanting conductive impurities using the gate electrode pattern as an ion implantation mask so that the impurities are also implanted in the lower portions of the wide trench regions which constitute the heads of the T-shaped isolation layers and are extended to both sides from the upper ends of the narrow width trench regions. A silicide layer is formed on the elevated source/drain regions.
The depth of the wide trench regions is preferably less than or equal to 1,000 xc3x85.
The semiconductor material layer is preferably grown using a selective epitaxial growth (SEG) method.
The silicide layer is one selected from the group consisting of a Ti silicide layer, a Ta suicide layer, a Ni silicide layer, a Co silicide layer, and a Pt silicide layer.
To achieve the third object, a semiconductor device comprising T-shaped isolation layers has narrow trench regions in the lower portions thereof and wide trench regions connected to the narrow trench regions and extended to both sides of the narrow trench regions in the upper portions thereof.
The semiconductor device can further comprise gate electrodes formed on an active region defined by the T-shaped isolation layers and source/drain regions formed by also implanting impurities in the lower portions of the wide trench regions which constitute the heads of the T-shaped isolation layers and are extended to both sides from the upper ends of the narrow width trench regions.
The source/drain regions are preferably elevated above the semiconductor substrate.
The semiconductor device can further comprise a salicide layer formed on the source/drain regions.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.